Hardware Implementation of Iterative Projection-Aggregation Decoding of Reed-Muller Codes.
Marzieh Hashemipour-NazariKees GoossensAlexios Balatsoukas-StimmingPublished in: CoRR (2020)
Keyphrases
- hardware implementation
- decoding algorithm
- parity check
- ldpc codes
- error control
- signal processing
- error correcting
- low density parity check
- hardware design
- fractal encoding
- reed solomon
- dedicated hardware
- software implementation
- efficient implementation
- fpga implementation
- field programmable gate array
- error correction
- hardware architecture
- image processing algorithms
- joint source channel
- pipeline architecture
- image binarization
- quadtree
- fpga device
- parallel architecture
- pattern recognition
- general purpose processors
- reed solomon codes
- general purpose