Hardware-efficient computing architecture for motion compensation interpolation in H.264 video coding.
Wen-Nung LieHan-Ching YehTom C.-I. LinChien-Fa ChenPublished in: ISCAS (3) (2005)
Keyphrases
- motion compensation
- video coding
- motion compensated
- video compression
- motion estimation
- interpolation filter
- motion vectors
- rate distortion
- bit rate
- motion field
- video quality
- video codec
- motion estimation and compensation
- video coder
- block matching
- block matching algorithm
- rate control
- hardware implementation
- compression efficiency
- low bit rate
- video coding standard
- macroblock
- video sequences
- video encoder
- hardware architecture
- three dimensional
- rate distortion optimization
- rate distortion optimized
- advanced video coding