Improving performance of nested loops on reconfigurable array processors.
Yongjoo KimJongeun LeeToan X. MaiYunheung PaekPublished in: ACM Trans. Archit. Code Optim. (2012)
Keyphrases
- systolic array
- parallel architecture
- parallel processing
- processor array
- reconfigurable architecture
- parallel algorithm
- low cost
- hardware implementation
- parallel processors
- programmable logic
- shared memory
- communication delays
- interconnection networks
- single processor
- field programmable gate array
- fine grain
- linear array
- antenna array
- embedded processors
- real time
- search algorithm
- general purpose processors
- neural network