A Low-Area Low-Power Column-parallel Digital Decimation Filter Using 1-Bit Pre-BWI Topology for CMOS Image Sensor in 40-nm CMOS Process.
Peng YinZhongjie WangYingjun XiaXiaoping ZengFang TangPublished in: Circuits Syst. Signal Process. (2022)
Keyphrases
- cmos image sensor
- low power
- low power consumption
- single chip
- cmos technology
- nm technology
- power consumption
- parallel processing
- low cost
- high speed
- analog to digital converter
- mixed signal
- power reduction
- image sensor
- dynamic range
- solid state
- low voltage
- digital signal processing
- power dissipation
- processing capabilities
- parallel computing
- application specific
- hardware and software
- super resolution