Hardware Architecture of Layered Decoders for PLDPC-Hadamard Codes.

Peng W. Zhang Francis C. M. Lau Chiu-Wing Sham

Published in: CoRR (2021)

Keyphrases

hardware architecture
decoding algorithm
hardware implementation
hardware architectures
error correction
processing elements
field programmable gate array
machine learning
information systems
signal processing
hadamard transform
artificial intelligence
associative memory