Architecture of an Efficient Area and Flexible Multi-CODEC Processor.
Ji Hwan ParkHee Ju ParkJeong Hun KimKyu-sam LimSuki KimPublished in: ICECS (2006)
Keyphrases
- parallel architecture
- management system
- real time
- multi processor
- highly flexible
- instruction set
- computation intensive
- parallel processing
- design considerations
- video coding
- network architecture
- multi core processors
- single chip
- ibm zenterprise
- resource manager
- memory hierarchy
- memory access
- software architecture
- high speed
- low cost
- database systems