Login / Signup
High-Speed Reduced Stack Dual Lock Circuits.
Nisrine Saadallah
Xiaohua Kong
Radu Negulescu
Published in:
ASYNC (2004)
Keyphrases
</>
high speed
low power
real time
frame rate
primal dual
concurrency control
significantly reduced
high speed networks
shift register
data mining
genetic algorithm
image processing
website
database systems
focal plane