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Verification of RTL generated from scheduled behavior in a high-level synthesis flow.

Pranav AsharSubhrajit BhattacharyaAnand RaghunathanAkira Mukaiyama
Published in: ICCAD (1998)
Keyphrases
  • high level synthesis
  • case study
  • search algorithm
  • parallel processing
  • parallel architecture
  • response time
  • model checking
  • formal methods