Design of Low-Power and Area-Efficient Square Root Carry Select Adder Using Binary to Excess-1 Converter (BEC).
Poh Yuin LynNor Azlin GhazaliMohamed Fauzi Packeer MohamedMuhammad Firdaus AkbarPublished in: RoViSP (2023)
Keyphrases
- low power
- logic circuits
- square root
- power dissipation
- high speed
- low power consumption
- single chip
- low cost
- power consumption
- vlsi architecture
- digital signal processing
- gate array
- cmos technology
- image processing
- power reduction
- analog to digital converter
- ultra low power
- image sensor
- arrival rate
- floating point
- data flow
- low voltage
- signal processing
- mixed signal
- cmos image sensor
- computer vision