Parallel Gauss-Seidel on a Torus Network-on-Chip Architecture.
Mohammad H. Al-TowaiqKhaled DayPublished in: J. Interconnect. Networks (2012)
Keyphrases
- network on chip
- multi processor
- packet switched
- interconnection networks
- routing algorithm
- single processor
- shared memory
- gauss seidel
- fault tolerant
- multi core processors
- massively parallel
- parallel computers
- data transfer
- network simulator
- parallel algorithm
- program execution
- processing elements
- distributed memory
- multistage
- power dissipation
- parallel architectures
- parallel architecture
- parallel processing
- computer architecture
- parallel implementation