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A 17-nW, 0.5V, 500S/s, rail-to-rail SAR ADC with 8.1 effective number of bits.

Rong-Zhou KuoHao-Chiao Hong
Published in: VLSI-DAT (2014)
Keyphrases
  • high speed
  • neural network
  • computational complexity
  • small number
  • maximum number
  • case study
  • multiscale
  • parameter estimation
  • fixed number