Compiler-assisted leakage-aware loop scheduling for embedded VLIW DSP processors.
Meng WangYi WangDuo LiuZhiwei QinZili ShaoPublished in: J. Syst. Softw. (2010)
Keyphrases
- instruction scheduling
- multithreading
- level parallelism
- constraint programming
- embedded systems
- embedded processors
- scheduling problem
- multiprocessor systems
- parallel processors
- signal processing
- list scheduling
- digital signal processor
- communication delays
- instruction set
- parallel machines
- general purpose
- parallel execution
- digital signal processing
- scheduling algorithm
- parallel programming
- multi core processors
- shared memory
- parallel processing
- parallel algorithm
- high speed