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A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS.
Woo-Rham Bae
Haram Ju
Kwanseo Park
Sung-Yong Cho
Deog-Kyoon Jeong
Published in:
A-SSCC (2015)
Keyphrases
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power supply
power consumption
high speed
phase locked loop
nm technology
low power
cmos technology
intelligent control
packet loss
feature selection
hd video
high frequency
silicon on insulator
differential equations
end to end delay
power reduction
high voltage