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FPGA synthesis for minimum area, delay and power.

Kuo-Rueih Ricky PanMassoud Pedram
Published in: ED&TC (1996)
Keyphrases
  • high speed
  • power consumption
  • field programmable gate array
  • low cost
  • hardware implementation
  • minimum cost
  • texture synthesis
  • program synthesis
  • power reduction
  • spanning tree
  • clock frequency
  • parallel hardware