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Performance improvement of nano wire TFET by hetero-dielectric and hetero-material: At device and circuit level.

Jyoti PatelDheeraj SharmaShivendra YadavAlemienla LemturPriyanka Suman
Published in: Microelectron. J. (2019)
Keyphrases
  • associative memory
  • significant improvement
  • high speed
  • levels of abstraction
  • semiconductor devices
  • nano scale
  • neural network
  • evolutionary algorithm
  • analog vlsi