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Allocating Physically Aware Embedded Memory Test & Repair Processor using Floorplan Info at the RTL Design Level.
Vinay Kumar
Bhrugurajsinh Chudasama
Bin B. W. Wang
Manish Arora
Bharath Shankaranarayanan
Published in:
VTS (2023)
Keyphrases
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embedded systems
single chip
hw sw
memory subsystem
design process
design space
memory management
main memory
design methodology
experimental design
computing power
memory hierarchy