Low-Power FIR Filter Design Using Hybrid Artificial Bee Colony Algorithm with Experimental Validation Over FPGA.
Atul Kumar DwivediSubhojit GhoshNarendra D. LondhePublished in: Circuits Syst. Signal Process. (2017)
Keyphrases
- low power
- single chip
- low power consumption
- high speed
- gate array
- low cost
- power consumption
- artificial bee colony algorithm
- power reduction
- digital signal processing
- fir filters
- logic circuits
- power dissipation
- real time
- filter design
- mixed signal
- cmos technology
- signal processing
- multiresolution
- vlsi implementation
- swarm intelligence