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Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size.
N.-C. Lai
Sying-Jyan Wang
Y.-H. Fu
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2006)
Keyphrases
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low power
power consumption
low cost
high speed
high power
single chip
clustering algorithm
wireless transmission
vlsi architecture
low power consumption
general purpose
vlsi circuits
logic circuits
cmos technology
gate array
power saving
energy dissipation
optimal allocation
computational complexity