An 8-bit 19 MS/s low-power 0.35 μm CMOS pipelined ADC for DVB-H.
Bernardo Palomo VázquezFernando MuñozRamón González CarvajalJ. R. GarciaFernando J. MarquezPublished in: Integr. (2012)
Keyphrases
- low power
- analog to digital converter
- mixed signal
- power consumption
- low cost
- high speed
- image sensor
- single chip
- vlsi circuits
- cmos image sensor
- digital video
- high power
- digital signal processing
- vlsi architecture
- cmos technology
- data flow
- low power consumption
- gate array
- real time
- video transmission
- wide dynamic range
- high definition television
- delay insensitive
- logic circuits
- multi channel
- nm technology
- embedded systems
- image processing