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Tb/s Polar Successive Cancellation Decoder 16nm ASIC Implementation.
Altug Süral
E. Göksu Sezer
Ertugrul Kolagasioglu
Veerle Derudder
Kaoutar Bertrand
Published in:
CoRR (2020)
Keyphrases
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hardware implementation
integrated circuit
design methodology
hardware architecture
circuit design
rotation invariant
transform domain
error concealment
fpga implementation