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Design of a 9-bit 1GS/s CMOS folding A/D converter with a boundary error reduction technique.

Jongyoon HwangDongjoo KimMun-Kyo LeeSun-Phil NahMinkyu Song
Published in: SoCC (2014)
Keyphrases
  • analog to digital converter
  • error reduction
  • machine learning
  • learning algorithm
  • low power
  • circuit design
  • data streams
  • active learning
  • small number
  • linear programming