Login / Signup
A 1.2 pJ/b 6.4 Gb/s 8+1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28nm CMOS.
Shuai Chen
Hao Li
Liqiong Yang
Zongren Yang
Weiwu Hu
Patrick Yin Chiang
Published in:
CICC (2013)
Keyphrases
</>
high speed
data sets
database
data structure
prior knowledge
power consumption
data collection
high dimensional data
high quality
data analysis
image data
data mining techniques
statistical analysis
synthetic data
shape variations
raw data
data acquisition
low cost
data sources
real time