A Cost-Effective Dynamic Partial Reconfiguration Implementation Flow for Xilinx FPGA.
Ahmed KamaleldinIslam AhmedAbdulfattah Mohammad ObeidAhmed ShalashYehea IsmailHassan MostafaPublished in: NGCAS (2017)
Keyphrases
- cost effective
- hardware implementation
- hardware architecture
- low cost
- field programmable gate array
- fpga implementation
- high speed
- dedicated hardware
- fpga device
- cost effectiveness
- data center
- fpga technology
- efficient implementation
- parallel computing
- hardware design
- pipelined architecture
- hardware description language
- reconfigurable hardware
- software implementation
- hardware architectures
- computational intelligence
- real time
- parallel architecture
- single chip
- image processing algorithms
- low power
- flow field
- dynamic environments
- environmentally friendly