A 0.2-to-2.0GHz 65nm CMOS receiver without LNA achieving ≫11dBm IIP3 and ≪6.5 dB NF.
Michiel C. M. SoerEric A. M. KlumperinkZhiyu RuFrank E. van VlietBram NautaPublished in: ISSCC (2009)
Keyphrases
- high speed
- silicon on insulator
- cmos technology
- power consumption
- nm technology
- normal form
- metal oxide semiconductor
- low power
- low cost
- functional dependencies
- frequency band
- power supply
- data model
- analog vlsi
- circuit design
- single chip
- real time
- bit rate
- focal plane
- database
- integrity constraints
- data management
- database design