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QPACE: power-efficient parallel architecture based on IBM PowerXCell 8i.

Heinz BaierHans BoettigerMatthias DrochnerNorbert EickerUwe FischerZoltán FodorAndreas FrommerClaude GomezGottfried GoldrianSimon Heybrock
Published in: Comput. Sci. Res. Dev. (2010)
Keyphrases
  • parallel architecture
  • power consumption
  • hardware implementation
  • pattern recognition
  • lower bound