Low-power hardware design for the HEVC Binary Arithmetic Encoder targeting 8K videos.
Fábio Luís Livi RamosJones GoebelBruno ZattMarcelo Schiavon PortoSergio BampiPublished in: SBCCI (2016)
Keyphrases
- low power
- hardware design
- power reduction
- video codec
- power consumption
- high speed
- low cost
- low complexity
- video compression
- hardware implementation
- video data
- fpga hardware
- bit rate
- video frames
- single chip
- rate distortion
- video coding
- video sequences
- video content
- motion estimation
- low bit rate
- computational complexity
- field programmable gate array
- non binary
- motion vectors
- floating point
- motion compensation
- power saving
- logic circuits
- general purpose