Low Bitwidth CNN Accelerator on FPGA Using Winograd and Block Floating Point Arithmetic.
Yuk WongZhenjiang DongWei ZhangPublished in: ISVLSI (2021)
Keyphrases
- field programmable gate array
- floating point arithmetic
- floating point
- hardware implementation
- high speed
- cellular neural networks
- parallel implementation
- computing systems
- image processing algorithms
- graphical models
- signal processing
- data processing
- fine grained
- database
- low cost
- database systems
- low power consumption
- image segmentation