Accelerating 128-bit Floating-Point Matrix Multiplication on FPGAs.
Fumiya KonoNaohito NakasatoMaho NakataPublished in: CoRR (2023)
Keyphrases
- floating point
- matrix multiplication
- message passing
- fixed point
- distributed memory
- square root
- matrix factorization
- floating point unit
- sparse matrices
- instruction set
- floating point arithmetic
- field programmable gate array
- interval arithmetic
- hardware implementation
- graphical models
- image registration
- np hard
- bayesian networks
- similarity measure