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Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction.
Nam Sung Kim
Krisztián Flautner
David T. Blaauw
Trevor N. Mudge
Published in:
MICRO (2002)
Keyphrases
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power reduction
cache misses
power consumption
clock gating
memory hierarchy
caching scheme
low cost
cloud computing
low power
cache hit ratio