A memory efficient IPv6 lookup engine on FPGA.
Da TongYi-Hua E. YangViktor K. PrasannaPublished in: ReConFig (2012)
Keyphrases
- memory efficient
- ip address
- iterative deepening
- hardware implementation
- campus network
- real time image processing
- field programmable gate array
- hardware design
- external memory
- fpga implementation
- high speed
- multiple sequence alignment
- verilog hdl
- hardware architecture
- data acquisition
- signal processing
- ip addresses
- multi dimensional
- low cost
- wireless sensor networks
- auto configuration
- computer vision