Dynamic voltage domain assignment technique for low power performance manageable cell based design.

Elone Lee Feng-Tso Chien Ching-Hwa Cheng Jiun-In Guo

Published in: ASP-DAC (2010)

Keyphrases

low power
single chip
low cost
power consumption
high speed
low power consumption
logic circuits
vlsi architecture
digital signal processing
gate array
ultra low power
design process
power dissipation
high power
cmos technology
real time
power reduction
delay insensitive
embedded systems
image processing