Login / Signup
Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology.
Vojin G. Oklobdzija
David Villeger
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (1995)
Keyphrases
</>
cmos technology
power dissipation
low power
spl times
user interface
image compression
design process
power consumption
digital images
single chip