Logic synthesis for low power using clock gating and rewiring.
Tak-Kei LamSteve YangWai-Chung TangYu-Liang WuPublished in: ACM Great Lakes Symposium on VLSI (2010)
Keyphrases
- low power
- logic synthesis
- logic circuits
- power reduction
- power consumption
- power dissipation
- low cost
- high speed
- multi valued
- cmos technology
- heuristic search
- image sensor
- digital signal processing
- power saving
- energy efficiency
- quantum computing
- energy saving
- inductive learning
- data center
- mixed signal
- distributed systems