A high performance full pipelined arquitecture of MLP Neural Networks in FPGA.
Antonyus Pyetro do Amaral FerreiraEdna Natividade da Silva BarrosPublished in: ICECS (2010)
Keyphrases
- mlp neural networks
- low power consumption
- fuzzy artmap
- parallel architecture
- low cost
- high speed
- radial basis function
- field programmable gate array
- hardware implementation
- multi layer perceptron
- real time
- distributed memory
- neural network
- power consumption
- low power
- incremental learning
- feature extraction
- data flow
- hardware design
- single chip
- parallel computers
- pairwise