Hardware-assisted power estimation for design-stage processors using FPGA emulation.
Sebastian HesselbarthTim BaumgartHolger BlumePublished in: PATMOS (2014)
Keyphrases
- field programmable gate array
- hardware implementation
- low cost
- power reduction
- parallel architecture
- power consumption
- hardware architecture
- multithreading
- parallel computing
- general purpose processors
- parallel hardware
- hardware design
- real time
- high end
- single chip
- software implementation
- computational power
- parallel processing
- low power
- hardware architectures
- parallel algorithm
- embedded processors
- clock frequency
- dedicated hardware
- low power consumption
- reconfigurable hardware
- digital signal processing
- programmable logic
- memory subsystem
- parallel architectures
- computing systems
- processing elements
- memory management
- fpga implementation
- high speed
- computing power
- shared memory
- parallel execution
- parallel computation
- hardware and software
- digital computer
- gate array
- instruction set
- fpga device
- image processing
- power distribution
- processing units
- parallel implementation
- computer systems
- signal processing
- multi core processors
- parallel processors
- computer architecture
- high performance computing
- image processing algorithms
- chip design
- efficient implementation
- data acquisition
- fpga technology