Sharing the instruction cache among lean cores on an asymmetric CMP for HPC applications.
Ugljesa MilicAlejandro RicoPaul M. CarpenterAlex RamírezPublished in: ISPASS (2017)
Keyphrases
- memory hierarchy
- cache misses
- level parallelism
- high performance computing
- processor core
- information sharing
- speculative execution
- prefetching
- main memory
- multimedia
- fault tolerance
- scientific computing
- transactional memory
- hit rate
- instructional design
- knowledge sharing
- multi core processors
- computing power
- instruction set
- message passing interface
- embedded processors
- power consumption
- data structure