Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate Design.
Henrique KesslerMurilo BohlkeLeomar S. da RosaMarcelo PortoVinicius V. CamargoPublished in: LASCAS (2022)
Keyphrases
- low power
- single chip
- high speed
- power consumption
- low cost
- low power consumption
- vlsi architecture
- power dissipation
- logic circuits
- digital signal processing
- mixed signal
- high power
- cmos technology
- vlsi circuits
- gate array
- design process
- image sensor
- low complexity
- power reduction
- nm technology
- circuit design
- multi view
- delay insensitive
- ultra low power