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Hypervisor Extension for a RISC-V Processor.
Jaume Gauchola
Juan José Costa
Enric Morancho
Ramon Canal
Xavier Carril
Max Doblas
Beatriz Otero
Alex Pajuelo
Eva Rodríguez
Javier Salamero
Javier Verdú
Published in:
CoRR (2024)
Keyphrases
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instruction set
application specific
operating system
high speed
computer architecture
virtual machine
floating point
parallel architectures
single processor
computation intensive
database
real time