A Model Checking Based Approach for Detecting SDN Races.
Evgenii M. VinarskiiJorge LópezNatalia KushikNina YevtushenkoDjamal ZeghlachePublished in: ICTSS (2019)
Keyphrases
- model checking
- process algebra
- formal specification
- temporal logic
- formal verification
- model checker
- temporal properties
- concurrent systems
- symbolic model checking
- partial order reduction
- formal methods
- computation tree logic
- automated verification
- finite state machines
- pspace complete
- bounded model checking
- epistemic logic
- reachability analysis
- asynchronous circuits
- transition systems
- timed automata
- finite state
- verification method
- linear time temporal logic
- modal logic
- deterministic finite automaton
- planning domains
- reactive systems