Impact of Power Density Limitation in Gigascale Integration for the SIMD Pixel Processor.
Sek M. ChaiAntonio GentileD. Scott WillsPublished in: ARVLSI (1999)
Keyphrases
- parallel processing
- single instruction multiple data
- high speed
- floating point unit
- parallel architectures
- power consumption
- parallel algorithm
- parallel implementation
- ibm power processor
- low power
- computational power
- highly parallel
- floating point
- parallel architecture
- data integration
- real time
- image pixels
- pixel wise
- massively parallel
- intensity values
- multithreading