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6.25-10Gb/s adaptive CTLE with spectrum balancing and loop-unrolled half-rate DFE in TSMC 0.18µm CMOS.

Haoran SunYinhang ZhangXi Yang
Published in: IEICE Electron. Express (2022)
Keyphrases
  • high speed
  • cmos technology
  • low cost
  • low power
  • analog vlsi
  • genetic algorithm
  • image sequences
  • image quality
  • circuit design