BRDS: An FPGA-based LSTM Accelerator with Row-Balanced Dual-Ratio Sparsification.
Seyed Abolfazl GhasemzadehErfan Bank TavakoliMehdi KamalAli Afzali-KushaMassoud PedramPublished in: CoRR (2021)
Keyphrases
- field programmable gate array
- recurrent neural networks
- parallel implementation
- least squares
- hardware implementation
- application specific
- hardware software partitioning
- real time
- hardware design
- video processing
- computing systems
- embedded systems
- standard deviation
- search algorithm
- sparse representation
- low cost
- parallel computing
- primal dual
- bayesian networks
- image processing
- hardware architecture
- databases