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Control-theoretic adaptive cache-fair scheduling of chip multiprocessor systems.
Huseyin G. Arslan
Yu-Chu Tian
Fenglian Li
Chen Peng
Minrui Fei
Published in:
Trans. Inst. Meas. Control (2018)
Keyphrases
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multiprocessor systems
control theoretic
multithreading
cache misses
access patterns
distributed memory
communication delays
prefetching
parallel computing
robot control
memory access
low cost
control architecture
memory subsystem
computational power