A pipelined architecture for DLMS algorithm considering both hardware complexity and output latency.
Tadaaki KimijimaKiyoshi NishikawaHitoshi KiyaPublished in: EUSIPCO (1998)
Keyphrases
- hardware implementation
- worst case
- computational complexity
- cost function
- np hard
- preprocessing
- k means
- detection algorithm
- dynamic programming
- input data
- pipelined architecture
- computational cost
- probabilistic model
- management system
- space complexity
- increase in computational complexity
- parallel implementation
- real time
- response time
- objective function
- artificial intelligence
- memory requirements
- fine grained
- similarity measure