Network on Chip for Parallel DSP Architectures.
Yuanli JingXiaoya FanDeyuan GaoJian HuPublished in: ICESS (2005)
Keyphrases
- network on chip
- interconnection networks
- multi processor
- packet switched
- multi core processors
- signal processing
- single processor
- routing algorithm
- parallel architectures
- shared memory
- fault tolerant
- parallel processing
- massively parallel
- parallel algorithm
- digital signal processing
- high speed
- network simulator
- multistage
- parallel computers
- parallel implementation
- message passing
- distributed systems