TLP-LDPC: Three-Level Parallel FPGA Architecture for Fast Prototyping of LDPC Decoder Using High-Level Synthesis.
Yi-Fan ZhangLei SunQiang CaoPublished in: J. Comput. Sci. Technol. (2022)
Keyphrases
- parallel architecture
- high level synthesis
- ldpc codes
- low density parity check
- shared memory
- message passing
- distributed source coding
- parallel processing
- hardware implementation
- decoding algorithm
- error correction
- turbo codes
- channel coding
- distributed video coding
- distributed memory
- fpga implementation
- pipelined architecture
- parallel implementation
- processing elements
- low complexity
- compressive sensing
- field programmable gate array
- belief propagation
- image transmission
- parallel computing
- hardware design
- error resilience
- rate allocation
- video transmission
- distributed systems
- vlsi architecture
- markov random field
- error concealment
- parallel algorithm