Model Checking Software-Defined Networks with Flow Entries that Time Out.
Vasileios KlimisGeorge ParisisBernhard ReusPublished in: FMCAD (2020)
Keyphrases
- model checking
- temporal logic
- formal verification
- formal methods
- symbolic model checking
- temporal properties
- formal specification
- finite state
- automated verification
- finite state machines
- model checker
- reactive systems
- verification method
- linear temporal logic
- pspace complete
- computation tree logic
- social networks
- epistemic logic
- bounded model checking
- partial order reduction
- reachability analysis
- transition systems
- software development
- concurrent systems
- timed automata
- process algebra
- software systems
- abstract interpretation
- web services
- planning domains
- domain independent
- deterministic finite automaton
- source code