Low-latency hardware architecture for cipher-based message authentication code.

Imed Ben Dhaou Tuan Nguyen Gia Pasi Liljeberg Hannu Tenhunen

Published in: ISCAS (2017)

Keyphrases

low latency
hardware architecture
message delivery
hardware implementation
high bandwidth
high speed
high throughput
real time
highly efficient
virtual machine
hardware architectures
stream processing
associative memory
source code
field programmable gate array
general purpose
signal processing
pattern recognition