A Minimal Adder-oriented 1D DST-VII/DCT-VIII Hardware Implementation for VVC Standard.
Yibo FanJiro KattoHeming SunXiaoyang ZengYixuan ZengPublished in: SoCC (2019)
Keyphrases
- hardware implementation
- discrete cosine transform
- signal processing
- efficient implementation
- hardware architecture
- dedicated hardware
- fpga implementation
- software implementation
- pipeline architecture
- field programmable gate array
- hardware design
- image compression
- pattern recognition
- image processing algorithms
- transform domain
- neural network
- parallel architecture
- parallel algorithm
- software engineering
- fpga technology