A low power 90-nm CMOS motion estimation processor implementing dynamic voltage and frequency scaling (DVFS) and fast motion estimation algorithm.
Nobuaki KobayashiTadayoshi EnomotoPublished in: ISCAS (2008)
Keyphrases
- low power
- power reduction
- high speed
- single chip
- cmos technology
- power consumption
- motion estimation
- low voltage
- low cost
- nm technology
- clock frequency
- energy dissipation
- gate array
- vlsi circuits
- mixed signal
- optical flow
- digital signal processing
- power dissipation
- cmos image sensor
- logic circuits
- image sequences
- ultra low power
- low power consumption
- image sensor
- block matching
- embedded systems
- wide dynamic range
- parallel processing
- video coding